Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
An example of such an FPGA is the Virtex-4™ FX available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. FPGAs use configuration memory. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
A serializer-deserializer (“SERDES”) to Framer Interface (“SFI”) may provide transport of data. The Optical Internetworking Forum (“OIF”) is an industry group that promotes the development of interoperable, inter-network specifications and associated technologies. The OIF put forth a Specification for SFI Level 4 Phase Two (“SFI-4.02”) following the SFI Level 4 Phase One (“SFI-4.01”) Specification. Generally, an SFI aggregates data bandwidths for payload data rates of about 10 gigabits per second (“Gb/s”) and higher. Unfortunately, the SFI-4.02 Specification is extremely constrained with respect to a variety of parameters, including lane-to-lane skew. Heretofore, implementing a design meeting the SFI-4.02 Specification was limited to Application Specific Integrated Circuits (“ASICs”), which, among other things, have a slower time to market and a higher cost with respect to lower volume applications than FPGAs.
Accordingly, it would be desirable and useful to provide an interface in a PLD that is capable of meeting at least approximately a 10 Gb/s data rate while having a lane-to-lane skew that at least meets that specified in the SFI-4.02 Specification.